1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device for synchronous commutation, which executes high-frequency operation.
2. Description of the Related Art
A low-ON-resistance characteristic has conventionally been regarded as important for a DC/DC synchronous buck converter used in a computer or the like to improve the efficiency. For this reason, a trench-gate-type MOS transistor has widely been used to form a DC/DC converter. However, along with the recent rise in operation frequency, not only a low ON resistance but also a decrease in switching loss is required. Hence, it is important for a MOS transistor of a DC/DC converter to decrease not only the resistance but also the capacitance. From this viewpoint, a trench-gate-type MOS transistor is not preferable because of its structure in which a gate electrode opposes a drain layer via a thin gate insulating film. With this structure, the area can hardly be reduced, and therefore, the parasitic capacitance between the gate and the drain is large.
In place of a trench-gate-type MOS transistor, an offset-gate-type MOS transistor has begun to be used to form a DC/DC converter. The structure of a conventional offset-gate-type MOS transistor usable for a DC/DC converter has been proposed in, e.g., Malay Trivedi et al., “Comparison of RF Performance of Vertical and Lateral DMOSFET”, ISPSD99, Proceedings, pp. 245–248. Jpn. Pat. Appln. KOKAI Publication No. 5-121739 also discloses an insulated gate semiconductor device. As an example, the structure proposed by Malay et al. is shown in FIG. 1. FIG. 1 is a sectional view of a MOS transistor.
As shown in FIG. 1, an n+-type source region 12, n-type LDD region 13, n+-type drain region 14, and p-type body region 15 are formed in the surface region of a p−-type epitaxially grown layer 11 on a p+-type substrate 10. A gate electrode 16 is formed on the body region 15 between the source region 12 and the LDD region 13. A source electrode 17 is formed on the source region and body region 15. A drain electrode 18 is formed on the drain region 14. A reach through layer 19 is formed to connect the source electrode 17 and substrate 10. A source electrode 20 is formed on the lower surface of the substrate 10.
According to the above-described structure, the source electrode 20 can be formed on the lower surface of the substrate 10 by preparing the reach through layer 19. For this reason, the parasitic capacitance or parasitic inductance of the MOS transistor can be reduced. As a consequence, the MOS transistor can have a low resistance and can be operated at a high frequency.
However, the reach through layer 19 is most generally formed by impurity diffusion. Hence, the width of the reach through layer 19 is inevitably relatively large. In some cases, the reach through layer 19 occupies about ½ the area of the entire MOS transistor. For this reason, when the reach through layer 19 is formed, the size of the MOS transistor becomes large.
In actual manufacturing, the gate electrode 16 and source electrode 17 must be separated by a relatively large distance. This is because the misalignment of masks to be used to form the gate and source electrodes is taken into consideration. Then, the width of the body region 15 immediately under the source region 12 increases. Hence, the resistance value of the p-type body region with respect to holes becomes large, and the ruggedness to avalanche current of the MOS transistor deteriorates.
Additionally, the drain interconnection layer is normally located on the gate electrode 16. The gate electrode 16 is adjacent to the drain electrode 18 in the horizontal direction and to the drain interconnection layer in the vertical direction. As a result, the feedback capacitance of the MOS transistor increases.